? vitesse semiconductor corporation rev. 1.0.1 - september 20, 2004 vitesse confidential - page 1 of 3 - VSC8201 design considerations for wake-on-lan compliance simpliphy? gigabit ethernet phy series application note introduction this application note describes how the VSC8201 single port gigabit ethernet phy should be used to design a wake-on lan complia nt pcm based network adapter. it is assumed that the reader is familiar with the pci terminology used in this document. wake-on-lan (wol) is a protocol used to wake up a pc remotely, i.e to put the system into a fully powered state (s0, working) f rom a lower power state. a wol compliant pci gigabit nic card must be capable of operating under the voltage and current constraints of the d3 (lowest p ower) power state. the pci bus has two power sources namely vcc (main) and vcc (aux). in the d3 power state, only the vcc (aux) is on and the syst em/ device is said to be in ?sleep? mode. in this state the devi ce should draw no more than 375ma of current and should be capable of detect- ing wake up events. the following wake-up events must be supported by a wol compliant gnic: ? detection of a change in network link state - the mac detec ts this by polling the mii registers of the ethernet phy. ? receipt of a network wake-up frame (required). ? receipt of a magic packet (optional). the major components of a gnic are the ethernet mac and the ethernet phy. of these two, the main source of power consumption is normally the phy. in 1000base-t mode, the current drawn by all in dustry standard phys is more than 375ma; and therefore, to mak e the network adapter operate under the d3 stat e, it is imperative that the phy does not link up in 1000base-t when in the ?sleep ?/d3 power state. in order to meet the above mentioned requirements under all condi tions, some changes need to be made to the phy hardware config u- ration, and the gnic software driver. these are described in the following sections. design considerations theory the VSC8201 has the following active high hardware control pins that define the link-up capability of the phy after reset# deas sertion: ? mode10 - default on-chip pull-up. ? mode100 - default on-chip pull-up. ? mode1000 - default on-chip pull-up. ? frc_dplx - default on-chip pull-up. ? aneg_dis - default on-chip pull-down. if all the pins are kept as no-connects on the board, then by default the VSC8201 always auto-negotia tes during the link-up pro cess and advertises 10/100/1000base-t half/full duplex capabilities. this configuration is acceptable for a gnic that is not wol comp liant, i.e. it does not have to support operation in the d3 pow er state. but for a wol compliant gnic, the VSC8201 must have an external pulldown on the mode1000 pin so that by default the VSC8201 advertises only 10/100base-t half/full duplex capabilities. this eliminates the possibility of a link up in 1000base-t mode and enables operation in d3 power state.
? vitesse semiconductor corporation wol rev. 1.0.1 - september 20, 2004 vitesse confidential - page 2 of 3 - once the VSC8201 is under software driver control, the dr iver can write to mii registers and enable 1000base-t operation. the gnic can go into d3 sleep mode in the following ways: ? acpi shutdown - in this case the driver configures the vsc8 201 into 10/100base-t operating mode by writing to the mii register s of the VSC8201 before the vcc (main) supply goes off. ? abnormal shutdown - in this case the main power vcc (main) is lost suddenly and driver does not configure the VSC8201 in 10/ 100base-t operating mode by writing to the mii registers of the VSC8201. it is assume d that on sudden loss of vcc (main) the ma c will reset the VSC8201 by dr iving a pulse on the reset # pin of the vsc8 201. upon deassertion of r eset# the VSC8201 re-reads the hardware configuration pi ns, which should be set as shown in figure 1 below. VSC8201 hardware configuration the mode1000 pin must be pulled down on the board so that 1000 base-t capability is not advertis ed by default during auto-negoti a- tion. VSC8201 software configuration by default the VSC8201?s advertisement cap abilities are defined by the hardware contro l pins. in order to change the default ad vertise- ment capabilities of the VSC8201 by writing to the mii registers, the control mu st be transferred from the hardware pins to the mii regis- ters. once the driver is loaded it must set mii register 28.2 (mode/d uplex pin priority select) of the VSC8201. after this the gnic d river can override the default settings of the auto-negotiation advertis ement by writing to mii registers 4 and 9 of the VSC8201. constraints the VSC8201 outputs a 125mhz clock for use by the mac or an ex ternal device on the board if needed. this clock is enabled only when the reset# pin of the VSC8201 is deasserted. VSC8201 is compliant with wol power requirements in 10 /100base-t operating mode with th e clk125 out put enabled. since the VSC8201 requires a reset (which is generated by the mac) after abnormal shutdown to reconfigure the VSC8201 to advert ise only 10/100base-t operating speeds, it may not be possible to supply the mac with 125mhz clock generated by the VSC8201 and sti ll be wol compliant under all operating conditions. if the mac requires that the clock be active in order to gene rate a reset pulse during abnormal shutdown, then the 125mhz clock from the VSC8201 should not be used. the 125mhz clock can be used as a refere nce clock for the mac on non-w ol cards where the reset# of the vsc8 201 is connected to the supply and not controlled by the mac. mac VSC8201 reset# mode10 aneg_dis frc_dplx mode1000 mode100 vcc(main) vcc(main) vcc(aux) vcc(aux) clk_mac clock source other than clk125 output from VSC8201 clk125 * this clock output should not be used as the reference clock for the mac if the mac requires an active clock to generate or reset. figure 1: circuit for wol compliant gnic using VSC8201
? vitesse semiconductor corporation wol rev. 1.0.1 - september 20, 2004 vitesse confidential - page 3 of 3 - alternatively, an external reset generator could be used to generate a reset pulse to the VSC8201 whenever an abnormal shutdown is detected. in this instance, the 125mhz clock output from the VSC8201 could be used as a clock source for the mac. for support, contact: epg_support@vitesse.com mac VSC8201 reset# mode10 aneg_dis frc_dplx mode1000 mode100 vcc(main) vcc(main) vcc(aux) vcc(aux) clk125 reset generator vcc(main) vcc(aux)
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